1. Field
One or more aspects of example embodiments of the present invention relate to high performance and high reliability CMOS technology.
2. Related Art
The capacitance of a chip can be roughly partitioned into backend-of-line (BEOL) and frontend-of-line (FEOL) capacitance. For higher performance and lower power, low BEOL and FEOL capacitance is desired. The BEOL capacitance may primarily be due to interconnects, while the FEOL capacitance may include the capacitance due to devices. It is desired that scaling of devices in every generation results in lower BEOL and FEOL capacitance.
A Fin Field Effect Transistor (FinFET) device capacitance may be partitioned into gate capacitance and parasitic capacitance. The gate capacitance is an essential component of the device operation, and while the gate capacitance may generally decrease with scaling, the parasitic capacitance may not necessarily decrease. In fact, of the various contributions to device parasitic capacitance, such as gate-to-sidewall fringe, gate-to-source/drain epi fringe coupling, gate-to-source/drain plug coupling (also referred to as MOL capacitance), etc., the fringe capacitance may not decrease with scaling.
The above information disclosed in this Background section is for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not constitute prior art.